Research and innovation

Fig. 1 Plot of the ASIC

Fig. 2 Photo of the fabricated chip 

Ultrasound Transceiver for 2D CMUT Front End (FE) Core integrated circuit (IC) is a device primarily intended to individually excite CMUT elements and to receive, buffer and amplify receiving signals from individual CMUT elements. CMUT FE Core has 256 CMUT elements connection points (CCP) subdivided into 4 apertures laid out as aperture matrix of 2 rows and 2 columns. Each aperture has 64 CCPs laid out as matrix of 8 rows and 8 columns. Each CCP is able to drive single CMUT element or to receive and amplify thesignal coming from a single CMUT element. CMUT FE Core has 64 75 Ω terminated inputs able to receive the transmitting pulse signals. CMUT FE Core 64 inputs are shared with 64 outputs. CMUT FE Core has 64 outputs able to drive 1.5 m long coaxial cable.

The 256 CCPs are multiplexed to 64 outputs by the internal multiplexing structure. The latter structure multiplexes each i-th CCP of j-th aperture to i-th output. 4 digital channels clocked by one clock provide the pixel selection data. The mode signal puts the CMUT FE to transmit or receive mode.

The CMUT FE core is capable to drive 16x16 matrix of CMUT elements simultaneously. The grid of the CCPs is distributed with 250 mm pitch. Each individual transceiver channel contains logic circuit, pulser to generate the excitation pulses of +50 V, preamplifier and protection circuit to protect the preamplifier during the transmit cycle. Average power dissipation is 60 mW per channel. Receive preamplifier has the input-referred noise density of 4 nV/sqrt(Hz).  Amplifier recovery time after TX pulse 0.3 μs.

IC Prototyping Service: Europractice;

Chip size: 5.25×5.25mm;

Technology: AMS 0.18μm HV 6M CMOS ;

Year: 2013;

Prof. habil. dr. Romualdas Navickas;

Assoc. prof. dr. Vaidotas Barzdenas;

Phd student Karolis Kiela;

Master student Marijan Jurgo.

Fig. 1 Plot of the ASIC

Fig. 2 Photo of the fabricated chip

A fully integrated 3.0 – 3.6 GHz LC-VCO with an ETSPC frequency divider is designed and fabricated in a 0.18 μm IBM 7RF CMOS technology. The total chip area, including the ESD protection circuits and pads, is 1.5×1.5 mm². The active part of this fabricated chip occupies only 0.65×0.65 mm². Using 4-bit switched capacitor block and linearly varying varactors, the LC‑VCO achieves a tuning range from 3.02 GHz to 3.55 GHz. The output signal of the LC-VCO is divided down through ETSPC divider, with divide values ranging from 2 to 256. The measurement results of the proposed LC-VCO with frequency divider show a phase noise better than -108.89 dBc/Hz @ 1 MHz offset from 3.6 GHz carrier and a total power consumption of about 212 mW for 2.49 dBm of output power.

IC Prototyping Service: MOSIS;

Chip size: 1.5×1.5mm;

Technology: IBM RF 0.18μm 6M CMOS;

Year: 2014;

Assoc. prof. dr. Vaidotas Barzdenas

Master student Marijan Jurgo